1. Field of the Invention
The present invention generally relates to a method for generating layouts of photomasks, and more particularly to a method for generating layouts of photomasks by optical proximity correction (OPC).
2. Description of the Prior Art
Integrated circuits (IC) are made of devices and interconnections. In the fabrication process of ICs, photolithography is one of the essential techniques. The main purpose of the photolithography is to precisely transfer layouts on photomasks to a photoresist layer on a semiconductor substrate. Generally, by performing the photolithographic process as well as other semiconductor fabrication processes, such as etching processes, ion implantations, depositions and so forth, complicated and sophisticated IC structures can be obtained.
With the continuous miniaturization of semiconductor devices and the remarkable advance in fabrication techniques of semiconductor devices, the conventional lithography process meets its limitation due to printability and manufacturability problems. To meet the requirements of device design rules which continue to push the resolution limits of existing processes and tooling, a double patterning technique (DPT) has been developed and taken as one of the most promising lithography technologies for 32 nanometer (nm) node and 22 nm node patterning, since it can increase the half-pitch resolution up to twice higher by using current infrastructures. Besides, three-dimensional or non-planar transistor technology, such as the fin field effect transistor (FinFET) technology, has also been developed to replace planar MOS transistors. Generally, patterned structures in a FinFET, such as fin structures, can be obtained by sidewall image transfer (SIT).
Although the above-mentioned technologies, i.e. DPT and 3-D transistor technology, have been widely adopted by the semiconductor manufacturers and successively overcome major drawbacks in the fabrication processes, there are still some problems needing to be solved. For example, in order to prevent or overcome optical problems, such as optical proximity effect, in photolithography processes and polishing problems, such as dishing phenomenon, in planarization processes, dummy patterns are often added to layout patterns of semiconductor devices through computer simulation at the beginning of the fabrication process. However, how to effectively distribute different dummy patterns and feature patterns over individual photomasks is still a major topic for study in the semiconductor field. As such, improved methods for generating layouts of photomasks continue to be sought.